A Novel Digital Neural Network Hardware Implementation

Abstract

A new algorithm for compact neural network hardware implementation is presented, which exploits the special properties
of the Boolean functions describing the operation of perceptrones (artificial neurones with step activation function). The
algorithm contains three main steps: the digitisation of the ANN mathematical model, the conversion of the digitised model
into a logic gate structure, and finally the hardware optimisation by elimination of redundant logic gates. A set of C++
programs has been developed based on the presented algorithm. The programs generate an optimised VHDL model of the
ANN implementation. This strategy bridges the gap between the ANN design and simulation software (such as specialised
ANN MATLAB tool-box) and the software packages used in hardware design (Viewlogic, Xilinx). Although the method is
directly applicable only to neural networks composed of neurones with step activation functions, it can also be extended to
sigmoidal activation functions.