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Rajinder Tiwari
Prof R K Singh


In this contribution, we present an efficient CMOS based operational amplifier which uses an arrangement to provide an extra bias current into a conventional CMOS differential input signals. This technique enhances the slew rate of an operational amplifier for a given quiescent current. The design of a high performance CMOS operational amplifier (op-amp) with level 3 parameters at 0.2μm CMOS technology, that makes the use of stacked (cascode) current source techniques. This innovative approach benefits the chances operated by full complementary implementations of well known sub-circuits, to enhance the speed of such an operational amplifier and to better organize and economize layout generation. Unlike conventional techniques such as the cascoding, which increases the gain by increasing the output resistance, the replica-amp technique increases the gain by matching the main and the replica amps. Among the advantages of the replica op-amp technique are low supply, high swing, and effectiveness with resistive loads. The maximum operating clock frequency of the sample-and-hold sub-module increases from 290 kHz to 1 MHz with a hold capacitor of 1 nF and dissipates a static power of 7.5 mW. The PSpice simulations of the op-amp shows a unity gain bandwidth of 40 MHz and a DC gain of 72 dB, when using a bias current of 100 μA and a load capacitance of 15 pF.

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