DESIGN AND EXPERIMENT A MODIFIED CLOCK GATED DUAL EDGE TRIGGERED SENSE AMPLIFIED FLIP FLOPS FOR LOW POWER AND HIGH-PERFORMANCE APPLICATIONS

Abstract

In this paper, a Modified Clock Gated Dual Edge Triggered–Sense Amplified (MCGDET-SA) Flip-Flop (FF) is used to improve the performance by reducing the power consumption. The power consumption obtained by decreasing the clock switching power, reducing the delay and avoids power leakage. Unlike various earlier gated FF, the proposed MCGDET-SA FF involves retention property to lower the consumption and to change the modes of the switch circuits from idle to active and active to idle. The power dissipation is obtained using feedback path improvement. In the clock gating method, less number of transistors is used to reduce the area of the silicon. The proposed sense amplifier FF minimizes the delay and increases the speed where it leads to decrease the power consumption more. This paper aimed to combine all above-said features and proposed a modified clock gated amplified flip-flop for low and high-performance application in VLSI. The proposed FF is simulated, and the results verified for various supply voltages. The experimental result shows more improvements regarding power consumption, delay performance comparing with the other FF architectures