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D.S.Shylu D.S.Shylu
D.Jackuline Moni

Abstract

The Dynamic comparator is a basic building block of all analog to digital converter architectures. The need for low power dynamic comparators is essential to maximize speed and power efficiency of the ADC architectures. Normally, dynamic latched comparators suffer from kick back noise effect. A novel dynamic latched comparators with clocked PMOS technique is proposed in this paper. Simulation shows that the power consumption and kickback noise effect of the proposed dynamic comparator is 952.4µW and 1.1mVwhich is very less when compared with the conventional dynamic comparators The area occupied by the proposed comparator is 0.00218mm2. The simulated kick back noise effect of the proposed dynamic latched comparator is about 80% less than the conventional dynamic latched comparator with 1.8V supply.

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