Vedic Multiplier Using Nikhilam Navatascaramam Dasatah Sutra - ModernVLSI High Speed Multiplier

Abstract

In recent years, digital devices require arithmetic units, particularly multipliers at high speed and efficiency due to the growing complexity in performing arithmetic operations. Conventional multipliers are unstable when operating on large amount of data leading to errors and time delay. Vedic mathematics can be used to satisfy these demands. The proposed algorithm aims at improving the speed and reducing the power consumption of the Vedic multiplier by modifying the Nikhilam NavatascaramamDasatah Sutra based multiplier. The Vedic multiplier is suitable for multiplying real and floating point numbers. The algorithm is simulated using Xilinx ISE and implemented in Virtex-V. The results when compared to the conventional multipliers show a 15% improvement in the speed and 10% improvement in power reduction and 5 % improvement in area for 4, 8 and 16 bit inputs.