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Saleh M. Abdel-hafeez
Anas S. Matalkah


With Migration towards low supply voltages in low-noise embedded SRAM designs, low-power, high-speed, and small physical cell area become more essential in VLSI devices. This necessitates sharing of power supplies and substrates with sensitive digital and analogue circuitry, which have large impacts on timing and power specifications of SRAMâ??s performance. A CMOS eight-transistor (8T) memory cell circuit for single and multi-port SRAM is proposed. The cell is based on the traditional cross-coupled invertors, but with an addition of two NMOS transistors for read buffer circuit. The read buffer structure is based on pre-charging the read bit-line during the low value of read clock and evaluating the read bit-line during the high value of read clock. This eliminates the use of sense amplifier with all its synchronization schemes (i.e. self-timing), which exploits a cost-effective of overhead circuitry, and more important reduces the power consumption. Consequently, the 8T cell memory of sizes less than 5k-bit storage capacity has smaller total silicon area than six-transistor (6T) cell memory with the same storage capacity by a rate of 6%, while it is larger by a rate of 13% otherwise.
Furthermore, the cell contributes to the operation both at high speed and at low power supply voltage with a comparable silicon size of 14% larger than 6T SRAM cell. The simulation results show that, the embedded SRAM of size 128-bit X 128-bit is operating at a maximum frequency of 200 M

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