ANALYSIS OF STANDBY LEAKAGE POWER REDUCTION BY V BODY CONTROL SYSTEM FOR CORE DEVICES

Abstract

In current technology of Very large scale
Integration (VLSI) has many advancement and
support high performance computing, core devices
and consumer electronics. The introduced new VLSI
technology reduces size of transistor, results in
powerful and compact wireless devices. The Control
of leakage power consumption is a major difficulty
one which faced in technology of CMOS circuit
design and implementation, especially in handheld
devices like cellular phones and PDA’s. Miniaturized
electronics have the leakage current in the active and
standby mode due to sub threshold leakage that
causes the high power dissipation. There are several
works have been carried out to achieve low power
consumption in CMOS VLSI circuits. In order to
resolve this problem, proposed research work
introduced a Vbody control system based on the Sleepy
Lector concept to reduce standby leakage power of
CMOS that generates an optimal reverse body-bias
voltage from leakage monitoring circuit. In addition
to, Vbody control system that comprises of several
clocking algorithms and techniques like Clock Gating
(CG), Energy Recovery Clock (ERC), and Clock
enable Sleepy Lector and Clock boosting Sleepy
Lector. Sleepy Lector reduces leakage current by
introducing sleep transistors and leakage controlled
transistor (LCT). Energy recovery circuit controls
current flow by setting low voltage drop across the
device. Clock gating offers reduction of clock power.
The proposed optimal Vbody