THERMAL AWARE PLACEMENT AND ROUTING USING MULTIPLY SUPPLY VOLTAGE OPTIMIZATION

Abstract

Power dissipation in the in an IC at a particular spot increase the thermal profile of the spot which leads to the failure of the IC. There are huge research which aims for the thermal reduction and accumulation. The work proposes and algorithm which effectively goes for thermal profile based placement and routing and the different blocks are mapped with different supply voltage so as to reduce the thermal profile which leads to the critical path variation and the conditions are verified to check the timing issues. This increases the white space and increase the routability of the architecture. This proposed algorithm is verified with the few bench mark circuits and the results shows that this leads to reduction in area and power and the same has been extended for the multiplier architecture which also report 60% reduction in area and 9% reduction in power. The implementation of the algorithm is done using matlab and the proposed VLSI architecture was implemented using FPGA and ASIC platform.