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T. Kanimozhi
Dr. D. Murali


This paper presents an asymmetrical cascaded multilevel H-Bridge inverter topology with reduced number of switches for increasing the number of output voltage levels. The proposed topology reduces the Total Harmonic Distortion (THD) level to below that of IEEE standard. Here, Phase Disposition (PD) and Alternate Phase Opposition Disposition (APOD) multi-carrier pulse width modulation (PWM) techniques are used to control the gating pulses. To produce the different pulse pattern for each switch, the decimal to binary conversion technique is employed. The proposed circuit is quite simple to analyze and it is suitable for medium and high power applications. Time domain simulations are carried out in Matlab/Simulink platform for 19- and 21-level multilevel inverter topologies. The results demonstrate that the THD level has been reduced drastically for 21-level inverter compared to 19-level inverter and the voltage wave form closely resembles sinusoidal which is the desired one.

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