MODELING OF PULSE-COUPLED NEUROHARDWARE

Abstract

Using Simulink© tool, the Complementary MOS (CMOS) modeling of Pulse-Coupled Neural Network is demonstrated. Compact architectures for computing XOR and Parity functions without the need for weight learning are explained. Any N-bit parity function can be simulated with N hidden layer neuron, by the conventional method. As N increases, the network size grows and becomes complex for Very Large Scale of Integration realization. So, the fully connected networks are tried, which needs only N/2 neurons in the hidden layer. The architectures are claimed to be suitable for hardware implementation, since the majority of weights are equal to +1 that obviates the need for multiplier. Finally the network is configured to solve Character Recognition application. It also exhibited a satisfactory performance accepting 10% noisy patterns.