DESIGN OF LINEAR RAMP GENERATOR AND DIGITAL ORA FOR AN AREA EFFICIENT HIGH SPEED ADC BIST
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This paper presents a design of linear ramp generator and a digital output response analyzer for an on-chip testing of analog to digital converter. Linear ramp signal has generated by the self-biased adaptive ramp generator design and applied to the converter for test pattern generation. The digital output response of an analog to digital converter for the ramp signal has analyzed through the fully digital output response analyzer for the primary non-idealities of a converter. Non-ideal parameters have described in hardware description language and simulated to exhibit the performance and feasibility of an analog to digital converter in testing. The final uncertainty of the analog to digital converter outputs has observed through the proposed test scheme which detects the static errors in the logical evaluation procedure.