Main Article Content
common mode voltage (CMV) and Circulating current (CC) minimization is one of the most important attentions in inverter fed drive. Diode-clamped multi-level inverter (MLI) enables higher output currents per phase, effectively increasing the power rating of the drive. Various switching operation in the inverter legs creates the better voltage profile and leads to the enabling of CMV and CC in the drive system. The induced CC flows between the apparatus neutral (N) to the supply ground (G) due to the existence of parasitic capacitance. This CC may cause potential danger especially when parasitic capacitance poses large. In the past, several conversion topologies and modulation techniques have been introduced with minimization of the circulation current. However, these techniques lead to complexity, high cost, low voltage profile and efficiency due to lower modulation parameters. This paper proposes PS, POD, PD carrier shifting PWM algorithms for diode clamped MLI to tumbling the circulating current within each phase of inverter legs. The performances of proposed algorithms, in terms of circulating current, total harmonic distortion, losses and efficiencies are analyzed theoretically. The theoretically analyses are validated via simulation and FPGA based experimental results.