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This paper indicates the four novel low power flip-flops collectively called novel energy recovery flip-flops to reduce the power dissipation in a clock network. The energy recovery clocked flip-flops enable energy recovery from the clock network, resulting in significant energy saving. The designed flip-flop operates with a single phase sinusoidal clock generated by an efficient power clock generator. A multiplier of 2 × 2 bit pipelined in 3 stages is designed. The schematic of the synthesized net list is generated and simulation results are presented for general D flip-flop and after replacing them by the designed SCCER flip-flop. The results show 43.56 % less power dissipation in compare to normal D flip-flop. In order to demonstrate the feasibility of energy recovery clocking, we integrated 64 energy recovery SCCER clocked flip-flops distributed across an area of 1 mm × 1 mm and clocked them by a single-phase sinusoidal clock through an 4 levels deep H- tree clock network. We report here that in H tree based clock network there is 90% of energy recovery for SCCER flip-flop over conventional flip-flop (HLFF).