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Several energy efficient adder designs have been proposed over the years to speed up the multiplication in digital signal processors. The selection of the specific adder improves the performance of the multiplier design. In this paper, we propose a comparative study of different adders for the generation of 3X term (Hard multiple) in radix-8 booth encoding. The focus of this paper is to explore the design aspects of various adder architectures for the implementation 3X term. We consider Ripple carry adder (RCA), Carry look ahead adder(CLA), Ling adder, Parallel prefix Ling adder, Conditional carry adder(CCA), Kogge-Stone(KS) adder and Sklansky(SK) adder for our comparison. These adders are simulated using ISE simulator with the VHDL structural coding. Cadence RTL complier with TSMC library 180nm is used to synthesize and analyze the cell area, power and delay. The experimental results imply that the Sklansky adder shows the improved performance over other architectures and saves energy ~50% for 64 bits implementation of 3X term.