A NEW APPROACH TO DESIGN AN ARITHMETIC LOGIC UNIT BASED ON ANCIENT VEDIC MATHEMATIC

Abstract

ALU is the cardinal functional unit in
digital signal processor and embedded system
devices which perform complex arithmetic and
logical functions. In this paper we propose an
ALU architecture (Vedic coprocessor) which is an
integral unit of arithmetic and logical unit such as
multiplication, division, square, cube, square root
and cube root units. Each and every unit has an
architecture based on unique Vedic math sutras.
This proposed ALU architecture overcomes the
existing drawbacks such as high delay, irregular
structure of combinational circuits and high
power dissipation. Vedic ALU is designed and
simulated in XILINX ISE simulator and
implemented using Spartan 3 FPGA. The
proposed ALU is equivalent to Vedic coprocessor
which increases the efficiency of multiprocessor
configuration system design