INVESTIGATIONS ON EMBEDDED PROCESSOR ARCHITECTURES FOR THE SPEED CONTROL OF SWITCHED RELUCTANCE MOTOR DRIVE

Abstract

This paper examines the features of various digital processors for implementing an intelligent speed control algorithm for switched reluctance motor (SRM) drive. The Hybrid Self Tuned Fuzzy Logic -Proportional and Integral (HSTF-PI) control algorithm is used for the implementation of the speed controller in different processor architecture. The embedded architecture considered for the analysis is Digital Signal Processor (DSP) (fixed and floating point), Field Programmable Gated Array (FPGA) and Advanced Reduces Instruction Set Computing (RISC) Machine (ARM) architectures. The processors are compared in terms of type of architecture, code generation technique, and speed and memory utilization for realizing the algorithm. The experimental results indicates that the merits of the advanced architecture.