Hardware design of low power non-binary LDPC coder based on FPGA for WIMAX standard over GF(2m)
B Raj Narain T Sasilatha
Worldwide interoperability for microwave access (WiMAX) is a family of IEEE 802.16 standard, which promise to provide high data rate over network with high density users. In digital communication, coding frameworks is an exhaustively used term all around recommending the screw up review code. The upside of error correction is a back-channel and the retransmission of data can routinely be kept up a vital segment from, at the cost of higher transmission limit necessities everything considered. Channel coding is the critical endeavors to envision and switch the transmission spoils of remote structures, must have a not too appalling execution with a particular extraordinary focus to keep up high data rates. In this paper, a low power non-binary low density parity check (LPNB-LDPC) coder over GF(2m) is proposed for WiMAX standard. In general, LDPC coder is consist of two units such as check node unit (CNU) and variable node unit (VNU). The hardware realization of CNU is a perplexing portion as it entails of complex modules such as fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and multiplier. We astounded those problem by modified CNU structure, in which, flexible FFT/IFFT and multiplier used to replace FFT/IFFT and multiplier. The flexible design reduces the reconfigurable design and their time. The proposed LPNB-LDPC coder is implemented on Xilinx tool with different FPGA families and objective to enhance the hardware features are hardware utilization, power co
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