ASYMMETRICAL MULTILEVEL INVERTER TOPOLOGIES TO REDUCE THE SEMICONDUCTOR SWITCHES AND DC SOURCES
Jiwanjot Singh Ratna Dahiya Lalit Mohan saini
In this paper two novel topologies of asymmetrical multilevel inverter have been presented. Each topology is based on the concept of additive and subtractive combination of different DC sources. The proposed topologies have same structure when two DC sources are used; but, for more than two DC sources, each topology has different structure, number of semiconductor devices and number of output voltage levels. Figure of merit (FOM) for multilevel inverter is defined in this paper and calculated for various topologies including the proposed topologies. For proposed topologies, new multi carrier sinusoidal pulse width modulation (MC-SPWM) has been adopted to generate the output voltage levels of an inverter. High number of levels have been obtained by using less number of DC sources and unidirectional semiconductor devices in comparison to existing topologies. In this paper, simulation is done in MATLAB/ SIMULINK environment. The output voltage, load current and total harmonic distortion (THD) has been calculated.
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