Journal of Electrical Engineering : Volume 19 / 2019 - Edition : 2

DESIGN OF FLOATING POINT ARITHMETIC UNITS AND ITS APPLICATION IN OFFLINE SIGNATURE RECOGNITION SYSTEM EMBEDDED ON FPGA

Authors:
Nallathambi RAMYARANI
Veerana SUBBIAH
Prabhakaran DEEPA
Domain:
building electrification
Abstract:
Floating point arithmetic circuits play an important role in scientific computing, signal and image processing applications due to its wide dynamic range and high precision. In this work, floating point Arithmetic and Logic Units (ALUs) architectures are designed, implemented on Field Programmable Gate Arrays (FPGAs) devices and utilized for signature recognition system. Synthesis results proved that log based unit provides faster computations, but increases the area compared with conventional floating point arithmetic units. Hence offline signature recognition system is designed using logarithmic single precision floating point arithmetic units and implemented on FPGA. The person’s signature is classified by Support Vector Machine (SVM) and Neural Network (NN) approach. From the simulation results of the signature recognition system, the person's signature can be identified based on the features. The synthesis results proved that support vector machine classifier occupied only 34% of the FPGA resources available compared with a neural network approach that occupied 68% of the total resources. The various stages of the signature recognition system are analyzed in Xilinx FPGA and MATLAB
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