ENERGY- AND RELIABILITY-AWARE MAPPING FOR NOC-BASED ARCHITECTURES
NARESH KUMAR REDDY
There has been broad research on Task scheduling and mapping on a Multi-Processor System on Chip (MPSoC). In any case, none considers the optimization of communication types, which can fundamentally in uence communication energy and performance. Proposed work targets ongoing ap-plications which are mapped dynamically on NoC based architectures. We address precisely the energy and reliability aware mapping issues for NoC based architectures and propose an e cient technique to solve it. Moreover, the proposed technique takes into consideration new applications to be added to the system with insigni cant inter-processor communication overhead. Ex-perimental results shows that proposed technique gains not only a signi cant reduction in communication energy but also improvement in reliability.
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