AN ENHANCED CARBON NANOTUBE FIELD EFFECT TRANSISTOR FOR VLSI CIRCUIT DESIGNING IN NANO TECHNOLOGY
P. Prakash K. Mohana Sundaram M. Anto Bennet
In the recent days, Complementary Metal Oxide Semiconductor (CMOS) is one of the most widely used technologies that is used to attain high density Very Large Scale Integration (VLSI) circuits with high energy efficiency. Reducing the size of the components that are used to design the circuit is an important and demanding task. For this purpose, some of the architectures and frameworks are designed in the existing works. But, it has some major drawbacks such as, increased area, higher power consumption, and required large number of transistors. In order to overcome these issues, this paper introduced a new design architecture based on the Nano technology. The main intention of this work is to reduce the size of the components that are used in the VLSI circuit design, and to increase the overall performance of the proposed system. After initializing the parameters, the P-type and N-type channels and the size of the transistors are estimated based on the layout design. Then, the number of components and its size are reduced in the proposed Enhanced Carbon Nanotube Field Effect Transistors (ECNFET) design. After that, the library is generated and the filtering is applied to eliminate the noise in the circuit. The novel concept of this paper is it modified the traditional structure of CNFET with reduced number of transistors. In experiments, the proposed architecture is evaluated in terms of performance and is compared with the traditional circuits to prove the betterment of the E
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