Design and Implementing an Area and Energy Efficient High-Speed Low-Complexity Mixed-Radix Variable Length FFT Processor
Subashini C Senthil Kumar K Anand M
For solving destructions interrelated to orthogonal subcarriers, one of the predominant transformation method used extensively in telecommunications and digital signal processing especially in OFDM systems is Fast Fourier Transformation (FFT). Reducing the complexity and increasing the speed of a process can be obtained by using a modified FFT processor. Complexity is reduced by minimizing the number of multipliers. A Mixed-radix algorithm incorporated with Single path Delay Feedback (SDF) pipeline FFT architecture is used whereas it can be obtained by reconfiguring the FFT processor as 128-256-512-1024-2048-4096 points to reduce the computational complexity in this paper. Wherever it improves the throughput using the mixed-radix processing blocks, the area power trade-off is done. The area utilization is diminished by using higher radix butterfly structures as Radix-25 additionally. The Mixed-Radix Single-path Delay Feedback (MR-SDF-FFT) processor is synthesized by cadence using an UMC 180-nm CMOS cell library. A perfect simulation is carried out and the results are verified. The performance is evaluated by comparing the obtained results with the proposed results
This article is written in Adobe PDF format ( .pdf file ).To view this article you need to download the file. Please rightclick on the link below and then select "Save
target as" to download the file to your harddrive.