VLSI IMPLEMENTATION OF VARIABLE BIT RATE OFDM TRANSCEIVER SYSTEM WITH MULTI-RADIX FFT/IFFT PROCESSOR FOR WIRELESS APPLICATIONS
Dhanasekar SUBRAMANIYAM Dr. Ramesh JAYABALAN
In this paper, a Variable Bit Rate 64 Subcarrier OFDM Transceiver system is implemented in FPGA and the Modified Multi-radix 64 point FFT/IFFT blocks present in the OFDM design is intended for immense throughput Wireless Personal Area Network (WPAN) applications. The Proposed OFDM architecture is transmitted with different input Bit patterns and modulated by orthogonal frequencies. To scale down the complications of the Twiddle factor multiplications in FFT/IFFT blocks, Radix-22, 23, 24 are devised in it. The FFT algorithm with Single-path Delay Feedback (SDF) structure is made by Vedic multiplier along with compressor adders, in order to decrease the hardware cost and gives better speed performance in the FFT multiplier. The OFDM Transceiver design is implemented using Xilinx Virtex2 xc2v500-6 fg256 FPGA board, acquires 52.4K gates and consumed Power is about 64 mW with the operating frequency of 197MHz. The Cadence Design Tool with 90nm CMOS technology is used only for FFT/IFFT section in OFDM transceiver system, which occupies 25% reduction in total gate count and 33.9% less in Power dissipation as related to other existing FFT algorithms. The Multi-Radix 64-point IFFT/FFT algorithm using Vedic Multiplier can achieve the throughput rate of 162 MS/s along with the working frequency of 162 MHz can be intended for WPAN applications.
This article is written in Adobe PDF format ( .pdf file ).To view this article you need to download the file. Please rightclick on the link below and then select "Save target as" to download the file to your harddrive.