Journal of Electrical Engineering : Volume 18 / 2018 - Edition : 2

Reducing reconfiguration overheads of a reconfigurable dynamic system using active run-time prediction

Authors:
hariharan
kannan
Domain:
digital appliances
Abstract:
The performance of the Field-Programmable Gate Array (FPGA) is largely affected by its reconfiguration overheads. For a dynamic system in which the nature of the system is unpredictable at design-time, these overheads are expensive in terms of performance. To reduce these overheads, architecture along with two algorithms is proposed which dynamically predicts and schedules the configuration. As a result, the time reconfiguration overhead is reduced to improve the performance. In most cases, the scheduling result obtained exactly matches with the system whose configurations are fetched from HS memory. This could be the near maximum achievable performance for any FPGA architecture, executing a dynamic application.
Download Article:
 
This article is written in Adobe PDF format ( .pdf file ).To view this article you need to download the file. Please rightclick on the link below and then select "Save target as" to download the file to your harddrive. Download Article
Jee homepage | Jee Archive | Hard Copy | Publishers | Contact